The present invention relates to a method for producing a semiconductor integrated circuit device. Particularly, the present invention is effective in its application to a method for producing a combined type semiconductor integrated circuit device wherein both a bipolar transistor and a metal oxide semiconductor field effect transistor (hereinafter referred to as "MOSFET") are integrated on a single semiconductor substrate.
Recently, technical developments have been actively for a bipolar-complimentary MOSFET ("CMOS" hereinafter) having both the high drivability of the bipolar transistor and the low power consumption characteristic of CMOS.
On the other hand, a one transistor type memory cell comprising one capacitor for information charge storage and one MOSFET for switching is widely adopted as a memory cell of a dynamic random access memory ("DRAM" hereinafter) because it occupies a small area on a chip so is suitable for high integration. The DRAM is composed of a memory cell array for storing information and peripheral circuits. The peripheral circuits involve an X (row), Y (column) address input buffer circuit for selecting a desired one bit (one memory cell) from the memory cell array and writing or reading out information with respect to the thus-selected memory cell, a decoderdriver circuit and a sense circuit. The memory cell array occupies about 60% of the chip area of a memory LSI, having an influence on the power consumption and yield of the memory LSI. The peripheral circuits determine operating conditions for the memory such as memory access time and the level of input and output signals. For the peripheral circuits of the DRAM there usually is adopted the CMOS technique which attains low power consumption and high integration. But, for speed-up of the memory access time, etc. it is advantageous to apply the bipolar CMOS technique to the peripheral circuits. This is because a bipolar CMOS composite gate, as compared with a CMOS gate, is larger in load driving force and permits high-speed charge and discharge of a large output load at a portion where fan-out is large or such a large capacity load as a word line. The application of the bipolar CMOS technique to the peripheral circuits of DRAM is described, for example, in IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 23, No. 1, February 1988, pp. 5-11, and Japanese Patent Publication No. 65696/1986.